Expert Viewpoint, VSIA Org
Challenges Continue in Mobile Segments

By Farhad Mafie, President & CEO, Savant Company Inc.

In less than ten years, we have put behind us the era of voice-only mobile phones that were using only one CPU, one DSP, and one Radio. Today’s 3G phones and Smart Mobile Devices (SMDs) are being designed with multiple CPUs, DSPs, many specialized analog/digital IPs, and several Radios with their associated antennas, all in an ergonomically acceptable and reasonably priced package. Boundaries among mobile handsets, PDAs, MP3 players, and similar products are continuously being redefined as features such as high-speed downloading, integrated megapixel camera sensor, more than 20MB of memory, WLAN 802.11, Bluetooth, GPS, MP3 players, IPv4/IPv6 dual stack support, gaming, hot swap slots for SD/MMC cards, MPEG-4 capability, email and web browsing, are becoming standard features on more and more mobile products.

Mobile phones and SMDs more than any other categories of products in the recent years have benefited from the advances in CMOS scaling, System-on-Chip (SoC) design methodologies, and System-in-Package (SiP) technologies to reduce the overall system cost and offering higher performance products for the end user. Three areas of (1) CMOS technology advances and RF integration, (2) new EDA tools for Analog and Mixed-Signal designs, and (3) portability and usability of Analog/Digital IPs play a significant role in the mobile phone chipset design, system cost and overall performance.

• Designers continuously trying to reduce the mobile phones bill-of-materials (BOM) by implementing many of the Radios, Analog RF parts, and power-management functions in deep submicron CMOS without adding process complexity. Some of the Radios in mobile phone such as the Bluetooth Radio have already been implemented in CMOS with sufficient performance. However, due to many issues such as low power supply voltage, inadequate matching of small components, and the absence of on-chip passive components (e.g., resistors, capacitors, etc.) with sufficient analog characteristics, the need for stand alone Analog parts as well as Analog IPs for Mixed-Signal SoC designs will continue to grow for some time in the near future.
• In mobile chipset designs, CMOS scaling and design automation tools have played a significant role in digital domain, however, in the Analog world designs are still limited to a few hundred transistors –with different sizes and performances— and the most common and widespread design automation tool has been SPICE and its variants. Only in the last few years, major EDA vendors have started augmenting their tools with some Analog/Mixed-Signal SoC design flow by offering top-down floor-planning, routing, chip assembly capabilities, etc., that are helping the designers when interfacing Analog and Digital blocks in their new Mixed-Signal SoCs.
• Due to the overall competitiveness of the mobile market and shortened design cycles, the need for easy to use (integrate) off-the-shelf Digital and Analog IPs is apparent more than ever. In this process, VSI Alliance (VSIA) has played a significant role in developing the technical standards required to enable the mix and match of Intellectual Property (IP) cores from multiple sources. VSIA’s guidelines and design documents for the data that an Analog IP provider should give an IP integrator has been one of the most widely used documents among the Analog IP developers and users.